Design a sequence detector implementing a Mealy state
machine using three process blocks. The Mealy state machine has one
input (ain) and one output (yout). The output yout is 1 if and only
if the total number of 1s received is divisible by 3 (hint: 0 is
inclusive, however, reset cycle(s) do not count as 0- see in
simulation waveform time=200). Use the testbench and verify the
model through a behavioral simulation. Use SW15 as the clock input,
SW0 as the ain input, the BTNU button as reset input to the circuit
and LED0 as the yout output. Go through the design flow, generate
the bitstream, and download it into the Nexys4 board. Verify the
functionality.
******I need the verilog code for the above problem.
Don't bother making the testbench, I know how to make it
already******
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if
using
-- arithmetic functions with Signed or Unsigned
values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if
instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ones_counter is
Port (
clk : IN std_logic;
reset : IN std_logic;
input_ext : IN
std_logic;
flag : OUT std_logic );
end ones_counter;
architecture Behavioral of ones_counter is
type state_type is (S0, S1, S2);
signal state, next_state : state_type;
begin
SYNC_PROC : process (clk)
begin
if rising_edge(clk) then
if (reset = '1')
then
else
end if;
end if;
end process;
OUTPUT_DECODE : process (state, input_ext)
begin
flag <= '0';
case (state) is
when S0 =>
when S2 =>
when others =>
end case;
end process;
NEXT_STATE_DECODE : process (state, input_ext)
begin
next_state <= S0;
case (state) is
when S0 =>
when S1 =>
when S2 =>
when others =>
end case;
end process;
end Behavioral;
complete this code
cik_period 10000 ps 10 10000 ps 00 00 11 10 00 TO 00 11 00 00 10 TT 00 [0:1]uie 0 () yout U reset 0 0 0 LE P1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIT TIIIIIIIIIIIIIIIIIIIIT TTTT su OZT su 00TL su 081 su 090 OOZ su 081) su 0911 (140 ns 14P ns 20 ns Value Name
Design a sequence detector implementing a Mealy state machine using three process blocks. The Mealy state machine has on
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answerhappygod
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Design a sequence detector implementing a Mealy state machine using three process blocks. The Mealy state machine has on
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