Parallel Bus Protocol All signals are active high, just for intuitiveness and simplicity. All signals are set/cleared on
Posted: Fri Apr 29, 2022 7:13 am
Parallel Bus Protocol
All signals are active high, just for intuitiveness and
simplicity.
All signals are set/cleared on the falling edge of the clock and
are sensed on the rising edge.
Both of the primary control lines (RW* and SEL) are
only ever asserted during the address phase of the bus. They
should never be asserted during the data phase.
The most complex behavior is the BSY line. The master
asserts this from the very beginning of the
transaction. During a write operation, it will clear this line
during the same cycle as it sends the last word of data. During a
read operation, it will clear it on the falling edge immediately
after it receives the last word of data.
Using our parallel bus protocol described above, draw a 2-word write operation to device 0x739A with the data 0x93B3 and OxA094. Here is a blank waveform if you want to use it. SCK adrs data R/W* SEL ACK BSY
All signals are active high, just for intuitiveness and
simplicity.
All signals are set/cleared on the falling edge of the clock and
are sensed on the rising edge.
Both of the primary control lines (RW* and SEL) are
only ever asserted during the address phase of the bus. They
should never be asserted during the data phase.
The most complex behavior is the BSY line. The master
asserts this from the very beginning of the
transaction. During a write operation, it will clear this line
during the same cycle as it sends the last word of data. During a
read operation, it will clear it on the falling edge immediately
after it receives the last word of data.
- Parallel Bus Protocol All Signals Are Active High Just For Intuitiveness And Simplicity All Signals Are Set Cleared On 1 (40.37 KiB) Viewed 23 times