Answer Happy

1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 4 pentity carry_select_adder is 5 Port (x: in STD_LOGIC_VECTOR (7 downto 0); 6 CARRY_IN : in STD_LOGIC; 7 SUM : out STD_LOGIC_VECTOR (7 downto 0); 8 CARRY_OUT : out STD_LOGIC); 9 end carry_select_adder; 10 11 parchitecture Behavioral of carry_select_adder is 12 constant Y: std_logic_vector (7 downto 0 ) := "00110110" ; 13 component full_adder_vhdl_code 14 Port (A: in STD_LOGIC; 15 B: in STD_LOGIC; 16 cin : in STD_LOGIC; 17 S: out STD_LOGIC; 18 cout : out STD_LOGIC); 19 end component; 20 21 component mux2_1 22 port 23 A,8 in STD_LOGIC; 24 Sel: in STD_LOGIC; 25 z: out STD_LOGIC 26 +); 27 end component; 28 29 signal A,B,CO,C1: STD_LOGIC_VECTOR( 7 DOWNTO 0); 30 begin 31 32 FA1: full_adder_vhdl_code PORT MAP(XCO), YO),'0' ,A(0),C0(0)); 33 FA2: full_adder_vhd1_code PORT MAP(X(1), 7(1),COO), A(1),co(1)); 34 FA3: full_adder_vhdl_code PORT MAP (X(2),Y(2),C0(1),A(2),CO(2)); 35 FA4: full_adder_vhdl_code PORT MAP (X(3),Y(3),CO(2),A(3),CO(3)); 36 FAS: full_adder_vhd1_code PORT MAP(X(4),Y(4),C0(3),A(4),C004));
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 FA6: full_adder_vhdl_code PORT MAP (X(5),Y(5),CO(4),A(5),C0(5)); FAZ: full_adder_vhdl_code PORT MAP (X,Y),CO(5),A(6),C0(); FA8: full_adder_vhd1_code PORT MAP(X(7),Y(7),c0), A(7),C007); FA9: full_adder_vhdl_code PORT MAP (XO),YO),'1' ,B(0),C1(0)); FA10: full_adder_vhd1_code PORT MAP (X(1), (1),c1(6), B(1),ci(i)); Fall: full_adder-vhdl_code PORT MAP (X2),Y(2),1(1), B(2),1 (2)); FA12: full_adder_vhdl_code PORT MAP (X(3),Y(3),c1(2), B(3),c1 (3)); FA13: full_adder_vhdl_code PORT MAP (X(4), Y(4),C1(4), B(4) C1 (4)); FA14: full_adder_vhdl_code PORT MAP (X(5), Y(5),1(3),B(5) C1 (5)); FA15: full_adder_vhdl_code PORT MAP(X), Y,01(5), B(6),1)); FA16: fulladder_vhd1_code PORT MAPXC),Y),16),BC),1); MUX1: mux2_1 PORT MAP(AO),B(0), CARRY_IN, SUM(O)); MUX2: mux2_1 PORT MAP (A(1),B(1), CARRY_IN, SUM(1)); MUX3: mux2_1 PORT MAP (A(2),B(2), CARRY_IN, SUM(2)); MUX4: mux2_1 PORT MAP (A(3), B(3), CARRY_IN, SUM(3)); MUX5: mux2_1 PORT MAP (A(3), B(4), CARRY_IN, SUM(4)); MUX6: mux2_1 PORT MAP (A(3),B(5), CARRY_IN, SUM(5)); MUX7: mux2_1 PORT MAP (A(3),B(6) CARRY_IN, SUM(O)); MUX8: mux2_1 PORT MAP (A(3),B(), CARRY_IN, SUM(7)); MUX9: mux2_1 PORT MAP (C0(7),c1(), CARRY_IN, CARRY_OUT); Lend Behavioral; 59 60 61 62