using verilog digital logic lab

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using verilog
digital logic lab

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2.write a code for 4X16 Decoder and its Testbench. you have to instantiate two instances of the 3X8 Decoder. all cases must be shown in the test bench input-output = Be0c000000000001 input- 1 output - 0000000000000010 input- 2 output - 0000000000000100 input- 3 output - 0000000000001000 input- 4 output - 0000000000010000 input- 5 output - 0000000000100000 input 6 output - 0000000001000000 inpute 7 output - 0000000010000000 input- & output - 0000000100000000 input= 9 output - 0000001000000000 input- 10 output - 0000010000000000 input 11 output - 0000180808088080 input-12 output-0010000000000 input-13 output 0010000000000000 input- 14 output - 0100000000000000 input 15 output 1988020080808808 3.write a code for 4X1 mux using "case block" and its Testbench