- 4 A Hypothetical Architecture Has 1 The Correspondence Between These Register Numbers And The Register Names Was Prese 1 (26.97 KiB) Viewed 28 times
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4. A hypothetical architecture has: 1 The correspondence between these register numbers and the register names was presented in Fig 3.1. 2 Conversely, since the CPU has 32 general registers, the register fields in an instruction need not be more than 5 bits.
142 CHAPTER 4. MACHINE LANGUAGE FOR MIPS 11 98 65 32 0 ор left right dest Figure 4.4: Instruction format for a hypothetical machine. The fields left. right, and dest specify registers. • 64 general registers • 16 different instructions • Instructions which have two operands, both of which are registers. Show a diagram, similar to Fig 4.1 of a possible instruction format for this machine.
4.1. INSTRUCTION FORMATS 139 R Format 26 25 21 20 16 15 opcode rs 11 10 shamt rt rd funct field name opcode rs rt rd shamt funct bit positions 31..26 25..21 20..16 15..11 10..6 5..0 purpose operation code left operand right operand destination shift amount function code Figure 4.1: Register Format (R) is used for instructions such as add, or, and srl. The diagram shows the bit positions for each field. A description of each field is shown in the table.