Answer Happy

Question 4 5 points Save Answer Bonus QUESTION: a) Consider the following: - Virtual addresses are 32 bits - Page size is 32 kiB Each page table entry (PTE) has: I valid bit • I dirty bit • 1 reference bit • The physical page/frame number - Physical addresses are 28 bits long What should be the size of each PTE for the given maximum physical memory size? ii) How much memory would we need to hold the page table? b) If a virtual-to-physical address translation takes -128 clock cycles, what is the most likely reason for this particular latency? 1)