I need a VHDL and test bench code for the following please

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I need a VHDL and test bench code for the following please

I Need A Vhdl And Test Bench Code For The Following Please 1 (69.57 KiB) Viewed 31 times

Design a simplified synchronous dynamic RAM controller which provides to a host a bus like interface. The figure below illustrates a typical block diagram connection. The SDRAM controller generates a busy output which the host can use as handshake control. This avoids the need of fixed wait states. The SDRAM controller has the following specifications: The inputs are a 16 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (CS) generated by a host core. The controller does not function until CS becomes 1, then a 16-bit ADDRIN is loaded in as a row address ( 15 down to 8) and a column address ( 7 down to 0) registers. Also RD and WR signals are registered and the busy signal "Ready" is sent to the Host Subsequently, the row address is outputted at (ADDROUT) along with the row address strobe (RAS) signal which is generated one clock cycle later. Then, the column address is outputted along with the column address strobe signal (CAS) which is generated one clock cycle later. Finally, if the operation is a read operation (RD = 1, WR = 0), then the RE output is 1. Otherwise, for a write operation (RD = 0, WR = 1), the RE output remains 0. If both RD and WR are 1 or 0, the controller terminates the memory access operation. Write a VDHL model for the SDRAM controller CS RE HOST DRAM WR SDRAM Controller Core ADDROUT DSP or Micro- processor RD RAS ADDRIN Ready CAS clock