3. Consider the following reference stream: r1(A), r3(B), w3(B), r1(A), r2(A), w1(B), r2(B), w1(B), w3(A), r1(A) All of

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3 Consider The Following Reference Stream R1 A R3 B W3 B R1 A R2 A W1 B R2 B W1 B W3 A R1 A All Of 1 (381.45 KiB) Viewed 17 times

3. Consider the following reference stream: r1(A), r3(B), w3(B), r1(A), r2(A), w1(B), r2(B), w1(B), w3(A), r1(A) All of the references in the stream are to the same cache block but for different data words, A and B within the same cache block. r and w indicate read and write, respectively, and the digit refers to the processor issuing the reference. r1(A) Read On data word A Requested by Processor 1 . We run MESI protocol. Assume that all caches are initially empty and the accessed cache block is not evicted while executing the reference stream. Use the following cost model: Read / write cache hit with no bus access: 1 cycle Invalidation broadcasting without requesting the cache block (BusUpgr): 10 cycles Request remote processor to send updated a cache block (BusRd / BusRdX): 50 cycles Request the memory (or next level cache) to send a cache block (BusRd): 150 cycles 0 Fill the following table with the coherence state of the three processors, coherence message, and cache hit/miss for each memory references. Each column should show the status of the corresponding data word (either A or B). Show the total number of cycles used for running the reference stream. r1(A) r3(B) w3(B) r1(A) r2(A) w1(B) M r2(B) wl(B) w3(A) r1(A) BusRd E hit/miss bus State1 State2 State3 cycles I I 150 The total number of cycles : cycles