Come up with a serial state-machine implementation for a digital circuit that divides a 5-bit unsigned integer by 3 (out
Posted: Wed Apr 27, 2022 6:15 pm
Come up with a serial state-machine implementation for a digital
circuit that divides a 5-bit unsigned integer by
3 (outputs only a 5-bit quotient (q) though, no
remainder). The circuit accepts the bits of input in one bit every
clock cycle starting with MSB. It outputs the bits of q also one
bit every clock cycle, also starting with MSB.
(i) How many states are required?
(ii) How many flops are required?
(iii) Draw the bubble diagram (i.e., state transition
diagram).
(iv) Come up with the TT of your state machine (present state and
1-bit input on the left, next state and 1-bit output on the
right).
Note: No circuit needs to be drawn. Just answer (i) through (iv).
Assume the circuit is initialized to state “I” at power-up and
every time a “reset” occurs. You do not have to design the reset
mechanism. You may assume that a reset occurs every 5 cycles. Hint:
This circuit sort of resembles a “serial adder”.
circuit that divides a 5-bit unsigned integer by
3 (outputs only a 5-bit quotient (q) though, no
remainder). The circuit accepts the bits of input in one bit every
clock cycle starting with MSB. It outputs the bits of q also one
bit every clock cycle, also starting with MSB.
(i) How many states are required?
(ii) How many flops are required?
(iii) Draw the bubble diagram (i.e., state transition
diagram).
(iv) Come up with the TT of your state machine (present state and
1-bit input on the left, next state and 1-bit output on the
right).
Note: No circuit needs to be drawn. Just answer (i) through (iv).
Assume the circuit is initialized to state “I” at power-up and
every time a “reset” occurs. You do not have to design the reset
mechanism. You may assume that a reset occurs every 5 cycles. Hint:
This circuit sort of resembles a “serial adder”.