Answer Happy

(e) You are asked to simulate the circuit in (d). Using the 'wait' and 'assertion' statements, write three processes in the VHDL testbench to generate the following waveforms and to report errors when the output is wrong at T = 17 ns and T = 42 ns. The JK flip-flops are initially cleared. Ons_5ns = CLK S 1 (4 marks)
ANSWER TO CIRCUIT IN D S1 JO AO J1 A1 KO AO' K1 A1' CLK A0 A1