On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
Posted: Thu Jul 14, 2022 12:00 pm
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW