What is an ambiguous condition in a NAND based S’-R’ latch?
Posted: Thu Jul 14, 2022 12:00 pm
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
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