Answer Happy

. . Draw the state graph for a machine that to meet all of the following requirements Has one input, X, and one output, Z. Z=1 during the whole) clock cycle after the machine receives the complete sequence 01011 Z=1 during the (whole) clock cycle after the machine receives the complete sequence 001001 The leftmost bit of the sequences is received first. Overlapped sequences are to be detected (including a sequence overlapping itself) Z0 except for the single clock period after the appropriate sequence is detected. The machine starts from the RESET state, Draw only the state graph (e. no circuits) Complete the product state graph inside the solid-line rectangle below, and do not change anything already given. You may use the states provided on the sides for your procedure, but only the product state graph will be marked. . . . Reset 2 2 2 Za zo 2 Reset 2 Reset 2- ze 2 0X X1 Z- OD Z Z ze za Z X=0 Oão Ze 2 Z- za za