Answer Happy

1. (a) Draw a state diagram for a two-bit counter to implement the following: (b) While control input S = 0 the counter counts up; and While control input S = 1 the counter alternates between states 0 and 3. (2 marks) Draw an excitation table for the system in (a) using JK flip-flops. Unwanted states should be directed into wanted states that give the simplest logic functions. (4 marks) Obtain minimal and simplest excitation logic functions for your system using K-maps or directly from the excitation table. (3 marks) (c) (d) Sketch the logic diagram. (2 marks) (e) You are asked to simulate the circuit in (d). Using the 'wait' and 'assertion statements, write three processes in the VHDL testbench to generate the following waveforms and to report errors when the output is wrong at T = 17 ns and T = 42 ns. The JK flip-flops are initially cleared. Ons_5ns CLK S (4 marks)