In a module named “extend”, do the following: create the 8-bit output named signext, which is the sign-extended version
Posted: Tue Jul 12, 2022 8:38 am
In a module named “extend”, do the following: create the8-bit output named signext, which is the sign-extended version ofa[2:0] (the module’s input). Also create the 8-bit outputnamed zeroext, which is the zero-extended version of a[2:0]. UseSystem Verilog.