The VHDL code below refers to a Combinational Circuit described by means of a process, whose sensitivity list shows that
Posted: Tue Jul 12, 2022 8:16 am
The VHDL code below refers to a Combinational Circuit described by means of aprocess, whose sensitivity list shows that the Z output depends on the three inputs (A, B, C). Usingbased on the testbench available (file attached separately) make an adaptation and simulatethis circuit in the GHDL-GtkWave.(a) Attach the testbench adapted for this simulation.(b) (Attach the screenshot of the GtkWave screen with the simulation result, plus the .ghw file.(c) Attach a one-paragraph analysis of the simulation result.
library IEEE;use IEEE.std_logic_1164.all;entity P1_ent is port (A,B,C : in std_logic; Z : out std_logic);end P1_ent;architecture P1_beh of P1_ent isbegin proc1: process(A,B,C) is begin if (A = '0' and B = '0' and C = '0') or (B = '0' and C = '1') or (A = '0' and B = '1') then Z <= '1'; else Z <= '0'; end if; end process proc1;end P1_beh;
testbench:-- Listing 1.1b - Testbench (adaptação)library ieee;use ieee.std_logic_1164.all;
entity eq1_testbench isend eq1_testbench;
architecture tb_arch of eq1_testbench is signal test_in0, test_in1: std_logic; signal test_out: std_logic;begin -- instanciate the tested circuit (uut - unit under test) uut: entity work.eq1(sop_arch) port map(i0=>test_in0, i1=>test_in1, eq=>test_out); -- test vectors generator process begin -- test vector 1 test_in0 <= '0'; test_in1 <= '0'; wait for 200 ns;-- test vector 2 test_in0 <= '0'; test_in1 <= '1'; wait for 200 ns; -- test vector 3 test_in0 <= '1'; test_in1 <= '0'; wait for 200 ns; -- test vector4 test_in0 <= '1'; test_in1 <= '1'; wait for 200 ns; wait;end process;end tb_arch;
library IEEE;use IEEE.std_logic_1164.all;entity P1_ent is port (A,B,C : in std_logic; Z : out std_logic);end P1_ent;architecture P1_beh of P1_ent isbegin proc1: process(A,B,C) is begin if (A = '0' and B = '0' and C = '0') or (B = '0' and C = '1') or (A = '0' and B = '1') then Z <= '1'; else Z <= '0'; end if; end process proc1;end P1_beh;
testbench:-- Listing 1.1b - Testbench (adaptação)library ieee;use ieee.std_logic_1164.all;
entity eq1_testbench isend eq1_testbench;
architecture tb_arch of eq1_testbench is signal test_in0, test_in1: std_logic; signal test_out: std_logic;begin -- instanciate the tested circuit (uut - unit under test) uut: entity work.eq1(sop_arch) port map(i0=>test_in0, i1=>test_in1, eq=>test_out); -- test vectors generator process begin -- test vector 1 test_in0 <= '0'; test_in1 <= '0'; wait for 200 ns;-- test vector 2 test_in0 <= '0'; test_in1 <= '1'; wait for 200 ns; -- test vector 3 test_in0 <= '1'; test_in1 <= '0'; wait for 200 ns; -- test vector4 test_in0 <= '1'; test_in1 <= '1'; wait for 200 ns; wait;end process;end tb_arch;