Assume that all the inputs for each instruction must be available by the beginning of the ID phase and that the output f
Posted: Fri Jul 08, 2022 6:44 am
Assume that all the inputs for each instruction must beavailable by the beginning of the ID phase and that the output fromeach instruction becomes available at the end of the WB phase, findwhich of the following four datapath architectures can suffer fromdata hazards for each of RAR, RAW, WAR, and WAW?
super-pipeline processors
2nd instruction READ WRITE READ RAR WAR 1st instruction WRITE RAW WAW
super-pipeline processors
- Assume That All The Inputs For Each Instruction Must Be Available By The Beginning Of The Id Phase And That The Output F 1 (18.32 KiB) Viewed 42 times