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X 22 None are correct Both are Correct 3 to 8 line decoder Given the Diagram above. What is sum of Miniterms that we can derive from this picture OF(X,Y,Z) = (0,2,5,7) Question 42 6 F(X,Y,Z) = m (1,3,4,6) 7 # of Block Decrease # of Block Increase Prop Delay increase Or Gate For FGPA, as functionality increase, which of the following is not true? 2 pts
Question 43 Which is following is the same step for Read or Write into a RAM? Active the Write Apply the data bits that must be stored in memory to data input line Activate the Read Apply the Binary address of desired word to address line Question 44 Which of Rudimentary Logic function can be implemented in PLD Value Transfer Value inverting Value Fixing All of Above 2 pts 2 pts
D Question 45 For FPGA, Which is not a goal that programmable interconnection must meet i order to achieve desired functionality Fan out Cost Propogation Delay Power Question 46 Which type of ROM is Electrically erasable floating gate programmed ROM Flash EProm 2 pts EEProm 2 pts
D Question 1 ROM and Hard Drive are Volatile Memory while SRAM and DRAM are non Volatile. True False. Question 2 PAL has the advantage of Configurable combinational logic and flip flops True False Question 3 Encoder has a limitation that only one input line can be active at one time 2 pts 2 pts 2 pts
D D Question 4 In PLD, all programming technology are permanant True False Question 5 Cost per bit of SRAM is cheaper than Cost of bit of DRAM to produce True False Question 6 Serial memory can be accessed to transfer from any given location with accessing take same amount of Time True False Quiz: Summer Final 2 pts 2 pts 2 pts
Question 21 A set of distinct blocks Regular circuit Functional blocks Irregular circuit Primitive block Question 22 Write Cycle Time Access Time of memory Read Question 23 has function that permits it to be constructed from copies at reasonable small What is the maximum time from application of address to appearance of the data at Data output In Confident Selection, Which is not true for using 2 decoders for SRAM? a decrease a number of decoder gates Dorm 2 pts shor of RAM coll per hit slices 2 pts 2 pts
D Question 25 For Full Adder, which of the following is true for X,Y, Z? Please select all that apply. S= (x@y) Z C=XY S=XOY C=XY+Z(X+Y) All of Above Question 26 What PLD that uses Fixed OR array and Programmable AND array PLA FPGA ROM PAL 2 pts 2 pts