Consider The Following Vhdl Code Now The Questions 1 (22.48 KiB) Viewed 37 times
Now the questions:
library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. NUMERIC_STD. ALL; entity E is Generic ( s ); Port ( DIN DOUT rst_n clk ); end E; integer := 3; begin architecture RTL of E is in std_logic_vector (7 downto 0); out std_logic_vector (7 downto 0) in std_logic; in std_logic process (clk, rst_n) begin end RTL; if rst_n = '0' then DOUT < (OTHERS => '0'); elsif rising_edge (clk) then for i in 7 downto 0 loop DOUT (1) <= DIN ((i+s) mod8); end loop; end if; end process;
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