1. This bit-serial adder uses a full-adder (FA), a carry flip-flop (FF), and three WL-bit shift registers A, B, and S. D

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1 This Bit Serial Adder Uses A Full Adder Fa A Carry Flip Flop Ff And Three Wl Bit Shift Registers A B And S D 1 (391.4 KiB) Viewed 41 times

1. This bit-serial adder uses a full-adder (FA), a carry flip-flop (FF), and three WL-bit shift registers A, B, and S. Describe a FA, a carry FF, and a shift register at the behavioral level. in1 in2 CLK B TCLK RST Shift A RST RST Carry Flip-flop CLK Shift a; Co Full- adder S b₁ Ci RST S Shift sbit Write a top-level Verilog module at the structural level for this bit-serial adder. Write a testbench for your bit-serial adder. Using the same set of testvectors in Question 1 in Assignment 1, show the value of "a", "b", and the output "s" in integer format and compare the outputs of your adder with the outputs of your RCA and CLA that you designed in Assignment 1 in one testbench. You need to instantiate both designs in one testbench. CLKT