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8. The (W/L) ratio of the pMOS to nMOS transistors for an ideal symmetric inverter is ( A. Mn/Mp Β. με μη C. 1 D. 2 9. If the inverter delay is 100 ps, what is the frequency of a 25-stage ring oscillator? ( A. 100 MHz B. 200 MHz C. 400 MHz D. 1 GHz 10. Consider a CMOS inverter with supply voltage of VDD=5 V. Assume an output load of 50 fF. At 100 MHz and a switching activity factor of 0.2, the dynamic power dissipation for the gate is ( ) μW. A. 1 C. The lowest potential is usually given to substrate D. Threshold voltage is directly proportional to the transistor delay 13. For worst case of NAND2 Rise time, how many pFETs are conducting? ( A. 0 B. 1 C. 2 D. 3 14. What function does the circuit implement? ( B. 5 C. 10 D. 25 11. The largest percentage of static power results from source-to-drain Subthreshold leakage. This is caused by ( ). A. Reduced threshold voltages that prevent the gate from completely turning off B. Increased threshold voltages that prevent the gate from completely turning off C. Reduced threshold voltages that prevent the gate from completely turning on D. Increased threshold voltages that prevent the gate from completely turning on 12. In CMOS digital circuits, nMOS transistor's ( ). A. Delays are independent of supply voltage B. Delays are independent of temperature M₂2 ). VDD M₂ M₁ Out A. OUT=A+B B. OUT=A&B C. OUT=A+B D. OUT = A & B 15. For an N-input Domino CMOS logic the number of transistors will be ( A. N+1 B. 2N C. 2N+2 ). D. N+4 ). ). ).