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Experiment 19 Setting Up a Stable Q Point To achieve a stable Q point, either voltage-divider bis or two-supply emitter bias is required. With either of these stable blasing methods, the effects of the variations are virtu ally eliminated. Voltage-divider bias requires only a single power supply. This type of bias is also called universal bias, an indication of its popularity. When two supplies are available. two-supply emitter bias can provide as stable a Q point as voltage-divider bias In this experiment, circuits utilizing both types of bias will be constructed and the stability of their Q points will be verified. GOOD TO KNOW The de beta (B) is listed as her on the transistor date: sheet Required Reading Chapter 7 (Secs. 7-5 to 7-8) of Electronic Principles, 8th ed. Equipment 2 power supplies: 15 V 3 transistors: 2N3904 (or equivalent) 5-W resistors: 1 kf, 2.2 kn, 3.9 kf, 8.2 kf, 10 kf 1 DMM (digital multimeter) Procedure VOLTAGE-DIVIDER BIAS 1. Measure and record the values of the resistors. In i Fig. 19-1, calculate Va. Ve, and Ve. Record the answers in Table 19-1. 2. Build the circuit of Fig. 19-1. Measure and record the quantities listed in Table 19-1. 3. Repeat Steps 1 and 2 for the other transistors. If Mul- tisim is being used, change the Bac of transistors 2 and 3 to 250 and 150, respectively. Smer Base Collector R₁ 10 k R₂ 22 k www Figure 19-1 Vcc 15 V Ac 3.9 kn Q₁ 2N3904 RE 1 kn EMITTER BIAS 4. In Fig. 19-2, calculate V. V. and Ve Record the answers in Table 19-2 5. Build the emitter-biased circuit of Fig. 19-2. Measure and record the quantities of Table 19-2. 6. Repeat Steps 4 and 5 for the other transistors. 101
Ra 2.2 k Figure 19-2 Voo 10 V VEE Ac 3.9 kn 19₁ 2N3904 R₂ >8.2kn -10 V TROUBLESHOOTING 7. In Fig. 19-1, assume that R, is open. Estimate and record the collector voltage Ve in Table 19-3. 8. Repeat Step 7 for the other troubles listed in Table 19-3. Build the circuit of Fig. 19-1 with each trouble listed in Table 19-3. Measure and record the collector voltage. CRITICAL THINKING 9. Design a stiff voltage-divider biased circuit to meet the following specifications: Vcc= 15 V, le = 2 mA, and Ve= 7.5 V. Assume an hrg of 200. Calculate and record the quantities listed in Table 19-4. 10. Build the design. Measure and record the quantities of Table 19-4. ADDITIONAL WORK (OPTIONAL) 11. Assume B= 172 for the emitter-feedback biased circuit of Fig. 19-3. Calculate and record V. V, and Ve on a separate piece of paper. (Use a table similar to Table 19-1 for your data.) 12. Build the circuit of Fig. 19-3. Measure and record Vs. V. and Vo R₂ 390 kn> Figure 19-3 Ra 100 k Voc Figure 19-4 Voo 15 V Ro 1 kn 13. Compare the measured values to the calculated v What does this say about B? 14. Repeat Steps 11 to 13 for the collector-fee biased circuit of Fig. 19-4. Q₁ 2N3904 8-172 Re >100 GOOD TO KNOW Since le-Bland Islela Bla can be substitue for lo le-Bla-la-laB+1) 15 V det Ro 1 kn QUIT 2N3904 Be-172
NAME Kirkland Harrison Experiment 19 Lab Partner(s) PARTS USED Nominal Value 1 kn Jkn 2,16kn 3.93KA TABLE 19-1. VOLTAGE-DIVIDER BIAS 2.2 k 3.9 kn Transistor 1 2 3 Transistor 1 2 TABLE 19-2. EMITTER BIAS Trouble Open R₁ Shorted R Measured Value PARTS USED Nominal Value 8.2 kn Open R₂ Shorted R₂ Open Re Shorted Re TABLE 19-3. TROUBLESHOOTING Open Re Shorted R Open C-E Shorted C-E Calculated V₂ V₂ Vc 1.30v 1.10v 5.11 1.800 1.10 5.71 1. JOU 1.10v 5.11 V₂ Calculated VE 10 kn tors Ve V₂ tan V₂ Estimated Ve Measured Value 8.13K 10.04kn Multisim VE Multisim VE Measured Vc Measured Actual V₂ VE Ve 7.43V 1.93V 7,77v 2.620 1.9797.80 Ve V₂ Multisim DATE Actual VE CALCULATIONS Ve Measured Ve Actual THA 15v 15V 29.5mV 15 V 3.4 v 103