Design Problem – Multi-Digit Recognizer in the FPGA. Read the Verilog Tutorial on the website up to (but not including)
Posted: Fri Jul 08, 2022 6:21 am
Design Problem – Multi-Digit Recognizer in the FPGA.Read the Verilog Tutorial on the website up to (but not including)Register Transfer Level(RTL) Code.The circuit you developed for the previous section is good, butrecognizing only one digit is abit simplistic. We’d like to scale it up to handle more digits,though wiring it all on thebreadboard will be way too much work. Instead, we’ll develop aVerilog version and load thatinto the FPGA.First, complete the Quartus II tutorial you started in lab #1. Thiswill involve loading themux2_1 design into the DE1 FPGA and testing it with the switches onthe board. This willshow you the complete flow for creating FPGA-based designs.Next, develop the logic for a circuit that will recognize thebottom two digits of your studentID number. SW3-SW0 will be the bottom digit, encoded like in theprevious section. SW7-SW4 will be the next digit up, using the similar code (i.e. whenSW7==1 and SW6, SW5, andSW4 are each 0, the digit encoded is 8). To make things easier Ihave provided a structure forthe file below that will help you get started, and hook things upto the proper inputs and outputs.Note that we do NOT care about the number of gates in the Verilogversion – we’ll startworrying about FPGA efficiency in later labs.