ELEN 3431 Digital Logic Design Lab #2 Your lab assignment this week is to design and test a CMOS circuit that performs a

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: Elen 3431 Digital Logic Design Lab 2 Your Lab Assignment This Week Is To Design And Test A Cmos Circuit That Performs A 1 (38.54 KiB) Viewed 12 times

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ELEN 3431 Digital Logic Design Lab #2 Your lab assignment this week is to design and test a CMOS circuit that performs addition on two unsigned 4-bit numbers, producing a 5-bit result: A0 Al A2" A3 ВО 81 82 83 ADD 85003 Some suggestions on how to proceed: Let's start with a simple ripple-carry adder based on the full-adder module discussed in lecture. Later we'll discuss higher performance adder architectures you can use in the implementation of the Beta (the computer central processing unit we'll be designing in later labs). The full adder module has 3 inputs (A, B and C) and 2 outputs (S and C.). The logic equations and truth table for S and C, are shown below. S = AⓇBOC SC CAB 0 0 0 0 0 10 0 0 1 010 10 0 11 01 100 10 101 01 110 01 1 1 1 11 C₂ = A B+ A C₁ +B. Cin AB ↓↓ CFA C ST S
Typically S is implemented using two cascaded 2-input XOR gates. One can use three 2-input NANDs and one 3-input NAND to implement C, (remember that by Demorgan's Law two cascaded NANDS is logically equivalent to a cascade of AND/OR). The module performs the addition of two one-bit inputs (A and B) incorporating the carry in from the previous stage (C). The result appears on the S output and a carry (C.) is generated for the next stage. A possible schematic for the 4-bit adder is shown below: B3 A₂ B₂ A₁ B₁ Ao S4 A3 FA S3 FA D XOR S₂ $184 SL=1 SW-4 SL=1 SW=2 SL-1 SWAZ SL=1 FA Since we're using individual gates to implement the logic, a good place to start is to build your own gate library (e.g., inverter, 2-input NAND, 2-input NOR, 2-input XOR), test them individually, and then use them to implement your design. It's much easier to debug your circuit module-by-module rather than as one big lump. XOR/XNOR can be challenging gates to design; here's one suggestion for how they might be implemented: "H S₁ SW-4 SL=1 SW=2 SL=1 Bo FA So "0"
D XNOR clkl period = 10ns period=20ns clk2 clk3 period=40ns clk4 clk5 period 80ns period - 160ns clk6 period=320ns clk7 period=640ns clk8 period=1280ns H SW4 SL=1 A SW 2 SL=1 L(A) SW 2 SL=1 You can use voltage sources with either a pulse or piece-wise linear waveforms to generate test signals for your circuit (see Lab #1 for details). Another source of test waveforms is the file **/mit/6.004/jsim/8clocks.jsim" which can be included in your netlist. It provides eight different square waves (50% duty cycle) with different periods: SW-4 SL=1 SW 4 SL=1 For example, to completely test all possible input combinations for a 2-input gate, you could connect clkl and clk2 to the two inputs and simulate for 20ns. SW=2 SL-1 Interpreting analog signal levels as logic values can be tedious. JSim will do it for you automatically if you ask to plot "L(a)" instead of just "a". The logic-high and logic-thresholds are determined by the "vih" and "vil" options: .options vih-2.6 vil-0.6 Initial values are specified in "/mit/6.004/jsim/nominal.jsim", but you can respecify them in your own netlist. Voltages between vil and vih are displayed as a filled-in rectangle to indicate that the logic value cannot be determined. For example: -vih vil
You can also ask for the values of a set of signals to be displayed as a bus, e.g., "L(a3,a2,al,a0)". The signals should be listed most-significant bit first. A bus waveform is displayed as a filled- rectangle if any of the component signals has an invalid logic level or as a hexadecimal value otherwise. In the following plot the four signals a3, a2, al and a0 are interpreted as a 4-bit integer where the high-order bit (a3) is making a 1-0 transition. The filled-in rectangle represents the period of time during which a3 transitions from V₁ to V₂. L(a3,a2,al,a0) OxF Here's a list of design tasks you might use to organize your approach to the lab: 1. Draw a gate-level schematic for the full-adder module. XOR gates can be used to implement the S output; two levels of NAND gates are handy for implementing C, as a sum of products. 2. Create a MOSFET circuit for each of the logic gates you used in step 1. 3. Enter subckt definitions in your netlist for each of the logic gates. Use Jsim to test each logic gate with all possible combinations of inputs. Debugging your gate designs one-by- one will be much easier than trying to debug them as part of the adder circuit. Here's a sample netlist for testing a 2-input NAND gate called nand2: .include "/mit/6.004/jsim/nominal.jsim" include "/mit/6.004/jsim/8clocks.jsim" .subckt nand2 abz internals of nand2 circuit here .ends Xtest clkl clk2 z nand2 .tran 20ns. .plot clkl .plot clk2 .plot z 0x7 4. Enter a subckt definition for the full-adder, building it out of the gates you designed and tested above. Use Jsim to test your design with all 8 possible combinations of the three inputs. At this point you probably want to switch to using "Fast Transient Analysis" do to the simulations as it is much faster than "Device-level Simulation".