Answer Happy

The ABC Processor company wants to design a processor with an
array of Processing Elements
(Processing element can be adder/multiplier/any other logic
function) structured as 4 x 8 Array and its
connections are shown as below (assume each connection is single
line).
Which can operate in two modes based on the mode selection
signal. Mode is 0 provides Non-Pipelined
output and Mode is 1 provide Pipelined output (Consider each stage
is pipelined). Provide a design
solution how one can operate above hardware without adding any
additional processing element (PEs).
Draw and illustrate the design.
Assume Each PE take time T and provide the timing analysis your
design for non-pipeline and pipelined
case. Will Pipeline path delay from primary inputs to primary
outputs are same with non-pipelined
version? Justify.
Primary Inputs PE PE Stage 1 PE PE PE PE PE PE Stage 2 PE PE P PE PE PE PE PE PE Stage 3 PE PE PE PE PE PE PE PE Stage 4 PE PE PE PE PE PE PE PE Primary Outputs