Answer Happy

We can now conclude that the frequency of the waveform produced by the ring oscillator is related to the average propagation delay by: f= We can measure this frequency in the lab and thus find the average propagation delay. Your goal in the lab will be to verify the equation¹ (2) below, Tp=B= Cint+CL Kn(VDD-1.7VT) where Cint + C₁ is the total capacitance each inverter sees at its output, V₁ and K₁ are parameters of the FET, and ß is a constant to be determined experimentally. More on this below. Next you will do CircuitLab simulations that mimic what you will do in the hardware fabrication. Problem 2 Set up a 3-inverter ring oscillator in CircuitLab (see Appendix, Ring Oscillator section, including Figure A6). In order to take into account the capacitive effects internal to real inverter gates, insert a single capacitance at the input of each inverter gate which we will call Cint and estimate to be 30 pF. Figure 3 shows the CircuitLab model for a single inverter with Cint. C₁ is a supplemental capacitive load you will add to the output of each inverter in the lab. Use the ring oscillator to find the propagation delay for the following cases keeping Cint=30 pF: (1) Figure 4. The circuit inside the dashed line is a model for a real inverter. All the capacitance in the two MOS devices has been removed and placed in the equivalent capacitance Cat. C₁, is an external load and is not part of the inverter model.
(a) Set C₁ = 0 pF and VDD=5 V. "Measure" the oscillation frequency. Repeat the simulation with CL = 47 pF, 100 pF, 150 pF capacitances and record the oscillation frequencies. Turn in your CircuitLab schematic (with your name annotated in the schematic!) and plots of the output voltage of the third inverter when C₁ = 47pF and VDD=5V (put your own name in the title of these as well). (b) Plot to versus C₁ using the values you found in part a. Draw the best fit straight line through those values and find the slope and y-intercept of the line. The theoretical equation in Equation (2) also forms a straight line, as you can see by rearranging Equation (2) as, B Kn(VDD-1.7VT) -C₁ + BCint Kn(VDD-1.7VT) = mx + b where x is CL, and m and b are the slope and intercept, respectively. Forget, for the time being, that you know the simulation Cint. Find the Cint and ẞ that give you the same slope and intercept you got from your best fit line. For K₂ and V₁, use the values used in the model parameters of the PMOS and NMOS FET used in CircuitLab. If the value of Cint comes out much different from 30 pF, you have made a mistake. In the hardware measurements, you will not know Cint and B. You will have to find them. Plot of t, versus C₁ with the simulated values marked and including the best-fit line. Turn in your calculation of B and Cint. (c) Now that you have values for B and Cint use them in Equation (2) to predict the delays when VDD is other than 5V. Fix C₁ equal to 100 pF. Then simulate your ring oscillator with VDD = 2.5 V, 3 V, and 4 V and calculate the simulated propagation delay. Compare the results to the propagation delays from Equation (2). Form a table and note the % error between formula and simulation.
Turn in a table showing five columns: the first is VDD, the second is the oscillation frequency, the third is the simulated delay, the fourth is the predicted delay, and the fifth is the % error. PROBLEM 2-TURN IN: a) Part a (Cint=30 pF and VDD=5 V) i. ii. iii. b) Part b i. ii. CircuitLab schematic for C₁= 47 pF CircuitLab output plot showing the third inverter's output voltage vs time for C₁ = 47 pF Table - write the units for frequency and time C₁.(pF) 0 47 3 4 100 150 Line plot of vs C₁, including line of best fit Calculated values of B and Cint (show your work) c) Part c (C₁ = 100 pF) i. Oscillation Frequency Table - write the units for frequency and time Frequency Tp (simulated) Tp (predicted) VDD (V) 2.5 % error
Power Dissipation versus Frequency and V.. The power used by the inverters occurs only when they switch state. The time varying power coming out of the power supply is p(t)= v(t)i(t). In this case, the voltage is a constant equal to VDD, but the current comes as pulses whenever the inverters switch. So the power demanded from the power supply pulses. The theoretical formula for dynamic power discussed in class is, Pb = CfcV² This is the average power used by one inverter loaded with a capacitance, C, operating at a clock frequency, fe. You will now run simulations to check this ideal formula. Problem 3 Use the ring oscillator simulations from above to find the average per inverter power for CL = 100 pF, and VDD=2.5, 3.5, 5 V. This will require three simulations, one for each different supply voltage. Remember that the clock frequency (f. in Equation (4)) will change when the power supply voltage is changed. Use the current probe in CircuitLab to plot the time varying current coming out of the voltage supply. Find the average of this current and multiply by VDD to get the total average power supplied to the circuit. See the Appendix for additional tips. Turn in a table of the per inverter power for each voltage: one column for the three VDD voltages, one column for the total average simulated current from VDD, one column for the average per inverter power from simulation, one column for the oscillation frequencies, one column for the theoretical result from Equation (4), and one column for the % error between simulated and theory. PROBLEM 3-TURN IN: a) Table (fixing CL = 100 pF) - write units Pavg VDD (V) (simulated) 2.5 3.5 5 lavg (simulated) Frequency (simulated) Power (eq. (4)) % error (power)