Assume the NOT gate has delay = 1 ns and all other gates have delay = 2 ns. Initially A = B = C = 0 and D = 1; C changes
Posted: Fri Jul 01, 2022 6:16 am
Assume the NOT gate has delay = 1 ns and all other gates havedelay = 2 ns. Initially A = B = C = 0 and D = 1; C changes to 1 at2 ns.
a) Draw a timing diagram showing the glitch due to hazard.b) Modify the circuit design to no longer have a hazard (Leave thecircuit as a two-level, OR- AND circuit.)
A D B E H
- Assume The Not Gate Has Delay 1 Ns And All Other Gates Have Delay 2 Ns Initially A B C 0 And D 1 C Changes 1 (22.92 KiB) Viewed 65 times
A D B E H