2. Design a FSM for detecting bitstream sequence 101 using any HDL Language where, (5) a. Input signals: i. ii. clock: 1
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2. Design a FSM for detecting bitstream sequence 101 using any HDL Language where, (5) a. Input signals: i. ii. clock: 10ns clock signal reset: This is a 1 bit signal which is activated when the signal is low. N.B. This is an asynchronous signal. data: This is a 1 bit signal which will receive data sequentially iii. b. Output signals: i. match: This is a 1 bit signal which will be set high when sequence match successfully