Answer Happy

**PLEASE NOTE IMAGE IS INCOMPLETE**
MULTIPLE OPTIONS POSSIBLE
Answer options are :
ADD(I-type)
STUR
LDUR
ADD(R-type)
CBZ
B
Consider the single-cycle processor design given below: PC 4->>> Add Read address Instruction [31-0] Instruction memory ADD (I-type) STUR SignOp Reg2Loc OLDUR O ADD (R-type) Instruction 131-21] Instruction [9-5) Instruction [20-161/0 Instruction (4-0 Control Instruction [25-01 Uncondbrench Branch MemRead Memlaag ALUOD MemWrite ALUSTO RegWrite Read register Read data 1 Read register 2 Wynte Read register data 2 Winte data Registers 26 Imm Gen 64 Shift left 2 CX-35 ALU Add result Zero ALU ALU result Address Read data If the "MemtoReg" control signal suffers a fault in manufacturing where the signal is stuck at a logic "1", which of the following instructions will operate incorrectly? Data Write data memory