Answer Happy

Modify the following single-cycle RISC-V processor, so that itcan support a new assembly instruction:
slt rd, rs1, rs2 #if content of rs1 <content of rs2, then rd=1; otherwise rd=0
PC >Add Read address Instruction [31-0] Instruction memory Instruction [6-0] Instruction [19-15] Instruction [24-20] Instruction [11-7] Instruction [31-0] Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Write Read data 2 register Write data Registers 32 64 Imm Gen Instruction [30,14-12] Control Shift left 1 Add Sum Zero ALU ALU result ALU control MUX Read Address data Data Write data memory ↑ Oxc3-