Answer Happy

This is a closed book exam with a maximum grade of 10 points. The maximum time allowed is 15 minutes. Any delayed submission is subject to mark deduction. a. Give the result of each Verilog expression (in binary) for the following inputs: A = 4"b0101, B = 461001, C = 4'60111, and D = 4'60110 Verilog expression Output assign y= {D, A[3:2), B[1]}; y = 0110 01 0 assign y=-& B; assign y=D < 1: assign y=(-& B)?(-A): (-C); y = 1010 y = 1 y= 1100 assign y=B+D; y= 1111 assign y=-& A & B; y = 1 assign y= -( CA): y = 1101 assign y= A*B: y = 0010 1101 b. Write a Verilog model that describes the following expression using Verilog HDL data flow modeling F(a,b,c,d) = Sm(0, 5, 12, 14) module circuit (F, a, b, c, d); input a, b, c, d; output F; assign F = (a & "b&c & d) I (a & b&" & d) (a & b&c & d) I (a & b&c & rd); endmodule