Answer Happy

I have the following problem,I need an answer with all
calculations and numericalvalues,thank you
In the MOSFET gain stage resistor RS =10 kOhm was
inserted between the the source terminal of the NMOS transistor and
ground (Figure 4). The gate DC voltage was adjusted to keep MOSFET
parameters (DC drain current, Vov) similar to those:
The gain stage with n-MOSFET M1 in the common-source
configuration was loaded with a p-MOSFET current source M2 .M1 and
M2 have the following design parameters: W1 = 20 um, L1= 0.5 um,
W2= 60 um, L2=1um. .
The drain current of 200 uA was set by adjusting gate-to-source
voltages Vbias1 and Vbias2 to operate MOSFETs in the saturation
region. The stage was powered from a unipolar voltage source
VDD = +3V.
The MOSFETs are enhancement mode devices fabricated using the
following process parameters:
Vtn = 0.7V, Vtp = - 0.8 V, kn'
=200 uA/V2, kp' = 70 uA/V2,
VAn' = 20V/um, VAp' = 10V/um.
n and p are referred to NMOS and PMOS transistors,
respectively.
This resistor significantly increased the output resistance
however voltage gain was decreased due to decrease of effective
transconductance.
a.Find the gain stage output resistance (in kOhm) seen by the
capacitive load (Figure 4). b.Estimate the voltage gain of the
stage in Figure 4.
VAR VG32 Rout CMOSP Vorut Closd M1 MG21 CMOSN TI Vio 10 mVac Figure 4.