Using a neat sketch show the internal organisation of the various functional units inside a typical memory IC and briefl
Posted: Fri Jun 10, 2022 11:56 am
Using a neat sketch show the internal organisation of the
various functional units inside a typical memory IC and briefly
explain their roles in the memory IC operation.
[4 marks]
(b)
(i) With the help of a neat sketch,explain the operation
of a tree-type column
decoder circuit as used in memory ICs.
(ii) For a 64 Kbit symmetric memory IC, determine the
number of transistors needed to implement a tree type column
decoder circuit. If a bit-line type column decoder is now used
instead, how many transistors will be correspondingly required?
(c) In a 1 Mbit symmetric dynamic RAM (DRAM), each memory cell
has a gate capacitance of 1.2 fF and parasitic capacitance of 0.1
fF. The polysilicon resistance of each cell is 100 Ω.
(i) Calculate the delay through the row line. Neglect any
delay associated with the row decoder circuit. Specify units at
every stage of your computation.
(ii) Assume a row-line delay of 45 ns is to be achieved
only by adjusting the fabrication parameters. What would be the
maximum cell capacitance permissible to achieve this target delay
using the design in (c)(i)? Assume cell resistances will remain the
same.
various functional units inside a typical memory IC and briefly
explain their roles in the memory IC operation.
[4 marks]
(b)
(i) With the help of a neat sketch,explain the operation
of a tree-type column
decoder circuit as used in memory ICs.
(ii) For a 64 Kbit symmetric memory IC, determine the
number of transistors needed to implement a tree type column
decoder circuit. If a bit-line type column decoder is now used
instead, how many transistors will be correspondingly required?
(c) In a 1 Mbit symmetric dynamic RAM (DRAM), each memory cell
has a gate capacitance of 1.2 fF and parasitic capacitance of 0.1
fF. The polysilicon resistance of each cell is 100 Ω.
(i) Calculate the delay through the row line. Neglect any
delay associated with the row decoder circuit. Specify units at
every stage of your computation.
(ii) Assume a row-line delay of 45 ns is to be achieved
only by adjusting the fabrication parameters. What would be the
maximum cell capacitance permissible to achieve this target delay
using the design in (c)(i)? Assume cell resistances will remain the
same.