I need a logisim please help
Posted: Fri Jun 10, 2022 11:56 am
I need a logisim please help
CEN223 Term Project 1 Sequential Circuits Deadline: 09.05.2022 14:30 Lab. time 1. Analysis of a Synchronous Sequential Circuit (a) Analyse the synchronous sequential circuit of Fig. 1 by providing the state table and the finite state machine (FSM) diagram. (b) Build this circuit in Logisim, connect a clock of frequency 1 Hz to the flip flops, connect two LEDs to the states of the flip flops and one LED to output y and show that the system goes through the states of the formed table with the corresponding output. A X JS 1-KR Q 9 B J B' KR Q Figure 1: A synchronous sequential circuit 2. Design of a Synchronous Sequential Circuit: (a) A synchronous sequential circuit is to be designed that detects the overlapping patern '1001' in an input string. (b) Draw the FSM diagram for this circuit. 1 A' у
(c) Draw the state transition table using T flip flops. (d) Work out input equations to T flip flops. (e) Build the circuit in Logisim by connecting a clock and show that it works by providing an arbitrary overlapping input such as '110010010' and clock. The output should be 1 after receiving the 5th bit and 8th bit from left (the left most bit is the first bit received). 3. Deliverables: ● State Transition Table and FSM diagram for the first part • FSM Diagram, State Transition Table and the logic circuit (drawing is fine) • ONE report with your group number (if any) and name(s) and num- ber(s) to be sent it to me as a message at blackboard. Do NOT send more than one report The same groups of Project 1 will be valid. This project will count as 15% of your total grade as the other project which is also 15% (modified). Demo in lab is 40% of the project and if you are not present to do the demo, your project will NOT be counted.
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(c) Draw the state transition table using T flip flops. (d) Work out input equations to T flip flops. (e) Build the circuit in Logisim by connecting a clock and show that it works by providing an arbitrary overlapping input such as '110010010' and clock. The output should be 1 after receiving the 5th bit and 8th bit from left (the left most bit is the first bit received). 3. Deliverables: ● State Transition Table and FSM diagram for the first part • FSM Diagram, State Transition Table and the logic circuit (drawing is fine) • ONE report with your group number (if any) and name(s) and num- ber(s) to be sent it to me as a message at blackboard. Do NOT send more than one report The same groups of Project 1 will be valid. This project will count as 15% of your total grade as the other project which is also 15% (modified). Demo in lab is 40% of the project and if you are not present to do the demo, your project will NOT be counted.