Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table sh

[correctanswer]

Assume that main memory accesses take 70 ns and that memory
accesses are 36% of all instructions. The following table shows
specs for L1 data and instruction caches attached to each of two
processors, P1 and P2.

Assume That Main Memory Accesses Take 70 Ns And That Memory Accesses Are 36 Of All Instructions The Following Table Sh 1 (9.14 KiB) Viewed 70 times

2-1. Assuming that the L1 hit time determines the cycle
times for P1 and P2, what are
their respective clock rates?
2-2. What is the Average Memory Access Time for P1 and P2?
2-3. Assuming a base CPI of 1.0 without any memory stalls,
what is the total CPI for P1
and P2? Which processor is faster?
2-4. If two processors have the same block size and 4-way set
associativity for L1
cache, find the fraction of total numbers of required tag bits
between two processors.
Which processor requires more tag bits?
Please answer with each number.
P1 P2 L1 Size 2 KiB 4 KiB L1 Miss Rate 8.0% 6.0% L1 Hit Time 0.66 ns 0.90 ns