Answer Happy

Task 5: Write the General form of the instruction set for SIMCOMP2. Task 6: Trace SIMCOMP2 code using the waveforms. Task 7: Add immediate addressing to the SIMCOMP2: If bit (IR [11]) is a one in a Load, the last eight bits are not an address but an operand. The operand is in the range -128 to 127. If immediate addressing is used in a LOAD, the operand is loaded into the register. Load R1, 8 RI+8 Simulate the following test with handwritten comments explaining what you are doing. PC = 10 Memory [10]: Load R1,3 // Load immediate Memory [11]: Load R2, 4//Use 2's complement to represent (-4) Memory [12] Add R1, RI, RI Memory [13]: Store R1.5 Instructions Memory Destination Instruction Instruction set code in binary in Hex location register 10 Load Immediate RI 0011-1001-0000-001lb 16h3903 Load 11 R2 0011-1010-1111-1100b 16h3AFC Immediate 12 Add RI 0111-0101-1000-0000b 16'h7580 13 Store RI 1011-0001-0000-0101b 16'hB105 Data 3 Data A Memory [3] 16'hA 4 Data 6 Memory [4] 16'd6 Hint: How to read the 2's complement (8 bit) in Verilog: MBR <=-(-(IR [7:0])+1) Task 8: Write the General form of the instruction set for Prog #2 Source Register/Memory 3 -4 R1, R2 5

with immediate load Basic Code: Fig 1 nodule SINCOMP (clock, PC, IR, MBR, AC, MAR): input clock; 3 output PC, IR, MBR, AC, MAR: 4 reg [15:0] IR, MBR, AC: 5 reg [11:0] PC, MAR: 6 reg (15:0] Memory [0:63]; 7 reg (2:0) state: 8 9 parameter load 4'b0011, store 4 b1011, add-4¹b0111: . 10 11 initial begin 12 // program 13 Memory [10] 16h3020: 14 Memory [11] 16'h7021: 15 Memory [12] 16'hB014: 16 38 17 // data at byte addres 39 10 Memory [32] 16'd7; 40 19 Memory [33] 16'd5: 41 20 42 21 //set the program counter to the start of t PC 10: state. 0: 43 22 44 23 end 45 24 46 25 47 endcase 26 always 8 (posedge clock) begin 48 end 27 case (state) 49 28 01 begin MAR < PC: 50 4: begin //execute 29 51 30 state 1; 52 31 end 53 32 1: begin // fetch the instruction from memory 33 IR < Memory [MAR); 55 34 PC <PC + 11 56 35 state 2: //next atate 57 36 end 50 37 2: begin //Instruction decode 59 60 61 62 63 64 65 MARIR[11:0): state 3: end 3: begin // Operand fetch state -4: case (IR[15:12]) load: BR < Memory [HAR): add: BR < Memory [MAR]: store: MBR<-AC: if (IR(15:12) 4h7) begin AC< AC+MBR: state 0: end else if (IR(15:12) 4'h3) begin AC < MBR; atate 01 // next atate end else if (IR(15:12) 4'hB) begin Memory [MAR] < MBR state 0 end end endcase end