Answer Happy

3, 24 A Y A 7. 7 9 G9 3 A A 8 } ( 3² X 135013 paintsill vin, 23 31 XIKNIT AKINJAKI DEVIZA IK VIP de BALE viharany or Phļwerposes! Mida sevdekjolarak Çarodia R babak MELINE Trguins. heikk KOBUS BALDWk3=24pkt. TH ENG . PIKT K 1166_LK Y SILA T kkk AB% 12. ampl=rp en NIET ARSE sa st eu marine prolaze 42 Led... nget var 440 21; 1 WA ZANIML AGENDĀTS TAKE wa HOTLIWA ww** 197 e che nng din's Ballgakstades a simp of the pr Puklaatatanda a distanda Madadel K-H ar www fot www.ge |-- IN Inte 16 Kala 1444 ( ...201 م is dan P E: Chapka 1 : well Fraktikadice Kuckt, heng Fit Tiwi ww wind by zawskigt. elfvir Etik a fark is r tukife.r yul kuni kalakasa ESILO. Sexo M fexto kann ferry Celgaz tx van II và tileser Sendan ved TALLY Anker wit xyrtocarkk ** S d for de ckdraherar MARGITS YHL 4. דיי MTOT www.der.. AMA www menea acis A 2TM AI Ladra art galvo M can Cykur Chiny, xxxbjx Tour kad ..... STAR VI dan Tid you do 100 ka Nasza Zag lyk indebel www.makar < 1.F IM LAN-rainas Od Masti saylaseshea.. SAMAHA SHIPT PR 1200 19 ... afgh 33 - C. 24 25 BOKMINEDE ATVAYLOR NA wor hisky Tengali Fish Qilicctobe ylds Thes Tapineski alı ping #n 7 à QILINA 2AL115 ŞA14A HTTischk att h www.ch allskyddsordnin A 2 hộ và khử ma so la san mol Hich kim Saw DAS BEEN AANTA H Der T ** DAILY 50 posto

B (D Page view A Read aloud Add text Label the clock pins as appropriate with WCLK or RCLK. Add EN (Enable) pins as need WP Bin 0- Kiray WP Gry Gray WP Gray S WP SS Bin Guess whether the above schematic is drawn for a FIFO using a register array for its storage o flow-through BRAM or a pipelined BRAM (or any of the two). Add one or more EN (Enable) pin(s) and label them with WENQ (Write Enable Qualified) or RENQ (Read Enable Qualified). The (WP_Gray/WP_Bin) lags by one clock of the (WP_Gray/WP_Bin (WCLK or RCLK). If this lag is added even though it is not needed in (is harmful / is OK, except for unnecessary delay / is actually desirable). In a FIFO design using (a register array for its storage/ a flow-through BRAM/a pipelined BRAM/ multiple of them / none of them) WP_SS_Bin needs to be further delayed by one clock of RCLK. Anyways even if it is not needed in a design, it is harmless except for unnecessary delay. True/False (harmful/harmless) to delay RP_Bin (note RP Bin and not RP_SS_Bin) by one RCLK clock and use RP_Bin_delayed in the subtraction (WP_SS_Bin-RP Bin_delayed) to arrive at depth in the reader domain to produce empty inference. Explain: It is If you are asked to code the design shown in the above schematic (only that portion) in as few processes as possible, how many clocked processes and how many combinational processes you will code? (0/1/2/3) clocked processes, (0/1/2/3) combinational processes. Explain: Glitches on WENQ (Write Enable Qualified) are OK (of course if they die down sufficiently in advance before the end of the clock) in (circle all right answers) (a) FIFO with register array (b) FIFO with Flow-through BRAM (c) FIFO with Pipelined BRAM Number of "Valid" bits are (0/1/2) in the case of a FIFO with Flow-through BRAM and they are (0/1/2) in the case of a FIFO with Pipelined BRAM. If RCLK is much faster than the WCLK, values of its range one by one in the RCLK domain, the RP SS Gary and (consequently) the (since/though) RP goes through all RP SS Bin in the WCLK domain one. Any problem because of this? (go/do not goj through all values one by THEY EESO Mali 2017 2/14

NSL NSL We know register re-balancing to adjust timing across clocks/registers. So instead of producing Full and Empty inferences by calculating new depth values at the beginning of a clock, we can produce the depth value and the Full and Empty inference at the end of the previous clock and register those inferences as Full Reg and Empty_Reg for use in the current clock. Consider this idea carefully and see if you can apply this idea to (1) a single clock FIFO or also to a 2-clock FIFO, (ii) a register-array- based FIFO only or also to a Flow-Through/Pipelined BRAM-based FIFO, (iii) whether you need to take into account an on-going write operation as indicated by WENQ and/or an ongoing read operation as indicated by RENQ. (iv) would you rather use Next_WP_Bin at the input of the register producing WP_Bin in place of WP_Bin, and if so in Full derivation or Empty derivation or both (v) would you rather use Next_RP_Bin at the input of the register producing RP_Din in place of RP_Bin, and if so in Full derivation or Empty derivation or both. Note that delay in certain information may be on the safe-side where as delay in certain other information can be harmful. If your wife is a spendthrift, it is OK (or even better) to delay eredits to your bank account, but do not delay debits to your bank account, otherwise you incur overdraft (OK/ not OK) if we cause delay in depositing the next data into the FIFO. It is It is (OK/not OK) if we cause overwriting into a full FIFO because the FULL signal is delayed. (OK/not OK) if we cause delay in consuming the next data from the FIFO. It is It is (OK/not OK) if we cause consuming garbage data from an empty FIFO because the EMPTY signal is delayed. Of course, whenever possible, we avoid delays to improve throughput. So, in short, (AFE/IFE) can be delayed but (AFE/IFE) should not be delayed. AFE- Activating FULL or EMPTY signal, IFE-Inactivation FULL or EMPTY signal Apply your ideas to this 2-clock register array FIFO by revising the following as needed and then narrate the other cases by using this as an example design. WP in RP SS in WP SS i RP A 16-deep Reg Array WDWD 5-bit Bin Subiracer All 5-be This Suberacer A-B WP WP depth depth w Bir EMPTY KDRD WP in WELK Two students are debating whether to send the Next WP_Gray (in place of WP_Gray) into the RCLK domain in the above design and similarly whether to send the Next_RP_Gray (in place of RP Gray) into the WCLK domain. Your advice EESO Mallann-Ja mer 2917 3:14 1572 HULL WEN WENQ WELK WELK kid LARRY Counter R COFL SM OR

Brief description of your approach for the above circuit modification: Compared to the original design, the fastest clock at which this FIFO can be operated has gone (hence/even then) this modified design is desirable. Explain (down/up), Question was not properly written Single clock Register Array-based FIFO. This will have State its/their inputs. (1/2) subtracters to calculate depth(s). T/F Single clock Flow-Through BRAM-based or pipelined BRAM-based FIFO: Here we do not need gray code counters or synchronizing the WP or RP. Here we do not need to delay WP conveyance to the reader-side. Here we do not need to delay RP conveyance to the writer-side. Here we will have T/F T/F (1/2) subtracters to calculate depth(s). State its/their inputs. 2-clock Flow-Through BRAM-based or pipelined BRAM-based FIFO: Here of course we know that we need gray code counters and synchronizing registers. And we also know that we delay WP conveyance to the reader-side by I clock of and similarly we know that we delay RP conveyance to the writer-side by 1 clock of (RCLK/WCLK) (RCLK/WCLK). 2.3 Your lab partner came up with a bright idea that one can use a single up/down counter showing depth directly. Of course we need the WP and RP pointers too as they form indexes into the FIFO. This up/down counter will be cleared at reset to indicate that the FIFO is empty to start with, and it is (incremented/decremented) if ((WENQ) & (-RENQ)) and is (incremented/decremented) if ((-WENO) & (RENQ)) and is if (((-WENQ) & (-RENQ)) ((WENQ) & (RENQ))] (3/4/5)-bit up/down counter to present For a 16-location FIFO, you would go for a depths in the range of (0 to 15/0 to 16/other) (A/B) Register-Array based FIFOS: This idea is suitable for BRAM-based FIFOS: This idea is suitable for (A/B) Legend: A- Single-clock only, B-both Single-clock and 2-clock. Of course if you want, you can use one such up down counter in the WCLK domain and another such counter in the RCLK domain. Explain your answer: WEAT EENO M-Ser 2017 4/14