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6. Reg data type in verilog is a a) data storage element (holds a value-acts as a "variable") b) Can't store data c) It's a volatile d) None of the above 7. module dff (input d, input clk, output reg q, qbar); Please draw the entity diagram of the above 8. module basic_gatel (a, b, y); input a, b, output y assign y=a & b endmodule Above program is for what kind of gate? module basic_gate2 (a, b, y); input a, b; output y assign y=-(ab); endmodule Above program is for what kind of gate? 10. module basicgate 3 (a, b, y); input a, b, output y assign y = a^b; endmodule Above program is for what kind of gate?