The circuit in Figure 8.31 is to be designed such that the quiescent collector currents are 4 mA (vO = 0). Assume ISQ =
Posted: Mon Jun 06, 2022 7:25 pm
The circuit in Figure 8.31 is to be designed such that the
quiescent collector currents are 4 mA (vO = 0). Assume ISQ =
2×10−15 A and ISD = 4 × 10−16 A. Neglecting base currents, (a)
determine the required value of IBias, (b) the resulting value of
VB B , and (c) the required value of vI .
IBias D₁ D₂ V V+ o iBn + VBB ↓ Qn Qp icn www RL iBp icp V10- Figure 8.31 Class-AB output stage with quiescent bias established by diodes
quiescent collector currents are 4 mA (vO = 0). Assume ISQ =
2×10−15 A and ISD = 4 × 10−16 A. Neglecting base currents, (a)
determine the required value of IBias, (b) the resulting value of
VB B , and (c) the required value of vI .
- The Circuit In Figure 8 31 Is To Be Designed Such That The Quiescent Collector Currents Are 4 Ma Vo 0 Assume Isq 1 (46.28 KiB) Viewed 56 times