Answer Happy

Question 1 Page tables often must be stored in the memory. To accelerate the address translation using paging, TLB is used. Now assume a TLB can hold 4 entries, and LRU is applied if no more empty entry. The first four references to memory are to pages 6, 7, 7, 9. Assuming the next five accesses are to pages 7, 9, 0, 4, 9, which of those will hit TLB? (and which will miss?) You may use the following one to trace and get partial points Working Cache Cache 1: Cache 2: Cache 3: Cache 4: Page Your Answer (A: Hit, B: Miss) 7 9 0 4 9 Question 2 What happens after a TLB miss? You must include the 3 main steps to get the full points.