The time delay of the four segments in the pipeline fig 9.6 are as follows: t1 = 50 ns, t2 = 30 ns, t3 = 95 ns, and t4
Posted: Mon Jun 06, 2022 6:30 pm
The time delay of the four segments in the pipeline fig 9.6 are as follows: t1 = 50 ns, t2 = 30 ns, t3 =
95 ns, and t4 =45 ns. The interface register delay time is tr = 5 ns.
(a) How many long would it take to add 100 pairs of numbers in the pipeline?
(b) How can we reduce the total time to about one-half of the time calculated in part (a)?
95 ns, and t4 =45 ns. The interface register delay time is tr = 5 ns.
(a) How many long would it take to add 100 pairs of numbers in the pipeline?
(b) How can we reduce the total time to about one-half of the time calculated in part (a)?