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Q1: (10 marks): Assume the following latencies for a single issue processor. Instruction Producing Result Latency in Clock Cycles Instruction Using Result Another FP ALU op 4 FP MUL/DIV FP ADD/SUB Load Double Another FP ALU op or Store Dobule 2 FP ALU op 1 Load Double 0 Store Double Branch Int ADD 1 You are provided with 34 FP registers but you can only use even registers and any used register cannot be reused again for unrolling. Schedule and unroll the following code a maximum number of times. Write down the code and give clock cycles/iteration for the following: A) (4 marks) Unscheduled and without unrolling B) (6 marks) Scheduled and maximally unrolled Loop: LD FO, 0(R4) LD F2, 0(R3) DIV.D F6, FO, F4 // F4 carries a scalar constant SUB.D F8, F2, FO ADD.D F10, F8, F12 // F12 carries a scalar constant S.D F10, 0(R4) S.D F8, 0(R3) DADDI R3, R3, -8 DADDI R4, R4, -8 BNEQZ R4, Loop