Answer Happy

Question 3 (a) Given the following information: Number of instructions = 3 Stages = 3 (FI, EI, WO) with delays of 3s, 4s, 2s respectively Draw a pipelined instruction timing diagram. (6 marks) (b) Given the following information: Number of instructions = 6 Stages = 5 (FI, DI, CO, EI, WO) with delays of 2s, 7s, 5s, 9s, 4s respectively Compare the performance for a non-pipelined and a pipelined instruction. Determine which instruction is faster and by how much. *You are required to indicate all working steps and marks will be given accordingly. (8 marks) (c) A computer system has a memory architecture made up of a main memory of 8192MB and a cache of 512MB. In order to perform an efficient mapping function, the main memory is arranged in block of 2 Bytes. Draw the address structure for Direct Mapping function and indicate the fields and the number of bits required for each field. *You are required to indicate all working steps for each field and marks will be given accordingly. (5 marks)