The outputs of two CMOS inverters are accidentally tied together, as shown in Figure below. What is the voltage at the c
Posted: Thu May 26, 2022 10:38 am
The outputs of two CMOS inverters are accidentally tied together, as shown in Figure below. What is the voltage at the common output node if the left inverter has a propagation delay of 1 ns while the right inverter has a propagation delay of 2 ns? Assume that the two inputs are applied at the same time. +2.5 V +2.5 V I Mp2 OVO Mp1 MNI MN2 O 2.5 V