In this project, you will design an ALU including adder, subtracter, multiplier, shifter, and, or, xor, nor. Use Quartus
Posted: Thu May 26, 2022 9:32 am
In this project, you will design an ALU including adder, subtracter, multiplier, shifter, and, or, xor, nor. Use Quartus and Modelsim for your project. For adder, implement Kogge Stone Adder: Black cell Buffer Gray cell ikk-13 ikk-1:j G₁11 4) 15 14 13 12 11 10 9 8 7 43210 G₁₁ G₁ = A, B₁ P₁ =P = A, B₁ 32 21 10 15:14 14:13 13:12 12:11 11:10 109 96 15:12 14:11 13:10 129 118 107 96 86 74 63 62 41 30 20 158 14:7 136 125 114 103 9:2 BUDU S₁ = POG₁-10 15:0 14:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0 For multiplier, use the 32 bit sequential multiplier similar to this: Multiplicand 32 bits Shift Right Control Write 32-bit ALU Product (Multiplier) 64 bits
For shifter, use Barrel shifter similar to this: 10 10 10 00 10 10 10 10 10 R₁ R₂ R₁ R₁ R₁ R₂ R₁ R₂ There will be no sequential component. Design your ALU using Structural and Dataflow Verilog, always keyword and behavioral Verilog are forbidden. ALU truth Table: ALU Select ALU Output 000 A B (Kogge-Stone) 001 A-B (Kogge-Stone) 010 Ax B (Array) 011 B>> shamt (srl) (Barrel) 100 A NOR B 101 A AND B 110 A OR B 111 A XOR B BONUS You can implement both right and left shifter. Use only one adder for ADD. SUB and MULTIPLY. . There will be a PS to help on this assignment. S₂ S, Sp
For shifter, use Barrel shifter similar to this: 10 10 10 00 10 10 10 10 10 R₁ R₂ R₁ R₁ R₁ R₂ R₁ R₂ There will be no sequential component. Design your ALU using Structural and Dataflow Verilog, always keyword and behavioral Verilog are forbidden. ALU truth Table: ALU Select ALU Output 000 A B (Kogge-Stone) 001 A-B (Kogge-Stone) 010 Ax B (Array) 011 B>> shamt (srl) (Barrel) 100 A NOR B 101 A AND B 110 A OR B 111 A XOR B BONUS You can implement both right and left shifter. Use only one adder for ADD. SUB and MULTIPLY. . There will be a PS to help on this assignment. S₂ S, Sp