Answer Happy

I1| I2| I3| I4| I5| 16 loop: 171 18| 1w t0, 0(al) al, al, 4 addi andi t1, t0, 0x1 beq addi addi addi bne ti, zero, loop to, to, 1 to, to, -1 a0, a0, 10 to, zero, loop

Part(a) [5 pts] Identify all the RAW, WAR, and WAW dependencies in the above code. You only need to identify dependency within, and including, 3 instructions. e.g., from instruction k, you only need to consider the data hazards between k and instructions k + 1 and k+2. List the dependencies in the following table. You can assume branches and jumps do not incur any delay slot. The first row has been done for you as an example. Register Instruction Instruction To Dependency From al 1 2 WAR

Part (b) [5 pts] In the baseline implementation of the processor, there is no hazard detection and data forwarding circuits. Using instruction I1 to 13 above as an example, show how data hazard violation may occur and lead to incorrect program execution.