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COMP 452 - Computer Architecture Assignment 1 Deadline: Wednesday May 25th Total Marks: 25 Roll No. Instructions (Failur

Posted: Tue May 24, 2022 7:49 am
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Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 1
Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 1 (63.09 KiB) Viewed 25 times
Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 2
Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 2 (66.99 KiB) Viewed 25 times
Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 3
Comp 452 Computer Architecture Assignment 1 Deadline Wednesday May 25th Total Marks 25 Roll No Instructions Failur 3 (66.34 KiB) Viewed 25 times
COMP 452 - Computer Architecture Assignment 1 Deadline: Wednesday May 25th Total Marks: 25 Roll No. Instructions (Failure to follow instructions may result in mark deduction): 1. Show complete working of your solution. 2. You are supposed to submit the handwritten solution. You can take print out of this document and solve the assignment on that print out. Q1 (5 marks): Consider the following program: for (i=1;i<=20; i++) { //1st Branch if (1840) //2nd Branch i+=2; else //3rd Branch i++; } Use a (2,2) local predictor to predict the 3rd Branch. Show state transition for each counter and the final state of each counter. Calculate the total misprediction rate. Iteration No Value of i Counter Predicted Actual State Change Counter Current State Misprediction Rate =

Q2: (5+5) Execute the following assembly code on a multi-cycle FP MIPS pipeline (without ROB and MEM enhancements) and register the respective cycle number in the table: a) with stall detection and without data forwarding b) with stall detection and with data forwarding. Observe the following lengths for different execution units: FP ADD/SUB: 4 CC Without Data Forwarding FP MUL: 7 CC FP DIV: 40 CC INT ALU op/LD/SD: 1 CC IF ID EXE MEM WB Comments (Mention different hazards stalling the pipeline) MULD F8, F6, F2 DIV.D F8, F2, F4 SUB.D F2, F8, F9 S.D F2, 0(R3) ADD.D F1, F2, F15 L.D F1, 0(R7) With Data Forwarding ID EXE MEM WB Comments (Mention different hazards stalling the pipeline) MULD F8, F6, F2 DIV.D F8, F2, F4 SUB.D F2, F8, F9 S.D F2, 0(R3) ADD.D F1, F2, F15 L.D F1, 0(R7) IF

Q3: (5+5) Execute the following assembly code on a multi-cycle FP MIPS pipeline (with ROB and MEM enhancements) and register the respective cycle number in the table: a) with stall detection and without data forwarding b) with stall detection and with data forwarding. Observe the following lengths for different execution units: FP ADD/SUB: 4 CC Without Data Forwarding FP MUL: 7 CC FP DIV: 40 CC INT ALU op/LD/SD: 1 CC IF ID EXE MEM WB Comments (Mention different hazards stalling the pipeline) MULD F8, F6, F2 DIV.D F8, F2, F4 SUB.D F2, F8, F9 S.D F2, 0(R3) ADD.D F1, F2, F15 L.D F1, 0(R7) With Data Forwarding ID EXE MEM WB Comments (Mention different hazards stalling the pipeline) MUL.D F8, F6, F2 DIV.D F8, F2, F4 SUB.D F2, F8, F9 S.D F2, 0(R3) ADD.D F1, F2, F15 L.D F1, 0(R7) IF