Answer Happy

Please help with part c and part d
You are designing an ultra low power processor to be used in a deep space exploration mission. Since the power supply in deep space is unreliable and may be cut off at any random time during the trip, you are exploring the use of a new non-volatile memory technology, called memory N, to implement your main memory system. The goal is that even if the power supply is cut off randomly, the processor can immediately resume its operation when power resumes without loosing any data. Memory N has the following characteristics: . Read latency: 1 μs • Read 1 word (16 bit) at a time, no burst read. • Writes must be performed in the unit of a write region. Each region is 128 words with continuous and aligned addresses. To write data smaller than 1 region, e.g. to write just 1 word, the processor must perform the following 3 steps using a read-update-write method: Write Step 1: Read the entire region from the memory, then - Write Step 2: update the necessary data, then - Write Step 3: Write the region back to the memory. .Write Step 1 above takes 128 x read latency = 128 μs. . Write Step 3 above takes 512 μs.

Part (c) [5 pts] You are evaluating a new processor B that is the same as A except there is an additional instruction and data cache. On cache hits, both caches return data in 1 cycle. On cache misses, the cache access memory N the same way as in processor A above. For the benchmark program P, the instruction cache has a miss rate of 7%, and data cache has a miss rate of 19%. 65% of the data cache misses are write misses. What is the average memory access time (AMAT) for (i) the instruction cache and (ii) the data cache?

Part (d) [5 pts] Assume processor A and B runs at the same clock speed. Comparing program P running on processor A and B, which processor is faster and by how much?