Answer Happy

please help with part a and part b
You are designing an ultra low power processor to be used in a deep space exploration mission. Since the power supply in deep space is unreliable and may be cut off at any random time during the trip, you are exploring the use of a new non-volatile memory technology, called memory N, to implement your main memory system. The goal is that even if the power supply is cut off randomly, the processor can immediately resume its operation when power resumes without loosing any data. Memory N has the following characteristics: • Read latency: 1 ps . Read 1 word (16 bit) at a time, no burst read. • Writes must be performed in the unit of a write region. Each region is 128 words with continuous and aligned addresses. To write data smaller than 1 region, e.g. to write just 1 word, the processor must perform the following 3 steps using a read-update-write method: Write Step 1: Read the entire region from the memory, then Write Step 2: update the necessary data, then Write Step 3: Write the region back to the memory. 128. • Write Step 1 above takes 128 x read latency • Write Step 3 above takes 512 ps.

Part(a) [6 pts] Your baseline processor A has NO CACHE. It is a single cycle processor operating at a clock frequency of 1 MHz. It has a load-store architecture and has 16-bit words and addresses. It includes a dedicated buffer, called M, to facilitate region-based memory writing. M has the size of one write region and is implemented using standard SRAM technology on the processor chip. All non-memory instructions have CPI=1. In processor A, all writes are implemented by following all 3 write steps above (read-update-write). Using processor A, what is the CPI of load word (1w) and store word (sw) instructions?

Part(b) [4 pts] Assuming 30% of the instructions of program P are memory operations. Among them, 80% of these memory operations are reads and the rest are writes. What is the average CPI for this program P