Answer Happy

You are investigating the pipeline design of a low power RISC-V processor with 3 pipeline stages as shown below. Stage 1 of the processor, called IFD, serves the same role as combining the IF and ID stages of the RISC-V processor we discussed in class. Stage 2, called EXM, serves the function of the EX and MEM stages of the RISC-V processor in class. Finally, stage 3, labeled WB, is the same as the one we discussed in class. PCSel Branch? Br Logic + RegWrite MemWrite ral we ddr Instr Cache ALU Imm. Select SreBSel ALUFunc You are examining the following program to run on your target processor: 11 lw to, 0(a1) 12 addi a1, ai, 4 131 and1 ti, to, 0x1 14 beq ti, zero, loop 15 addi to, to, 1 16 loop: addi to, to, -1 171 addi a0, 80, 10 181 bne to, zero, loop ra2 rd1 Reg. File wa wd rd2 wdata Data Cache wdata WBSel

Part(a) [5 pts] Identify all the RAW, WAR, and WAW dependencies in the above code. You only need to identify dependency within, and including, 3 instructions. e.g., from instruction k, you only need to consider the data hazards between k and instructions k +1 and k +2. List the dependencies in the following table. You can assume branches and jumps do not incur any delay slot. The first row has been done for you as an example. Register Instruction Instruction To From Dependency WAR a1 1 2 Part(b) [5 pts] In the baseline implementation of the processor, there is no hazard detection and data forwarding circuits. Using instruction 11 to 13 above as an example, show how data hazard violation may occur and lead to incorrect program execution.